1. Field of the Invention
The present invention relates generally to a semiconductor device and a method for manufacturing the same, and more specifically, to a semiconductor device having a field effect element and a method for manufacturing the same.
2. Description of the Background Art
Semiconductor integrated circuits have increased the tendency of high density and have achieved high speed operation and low voltage of power supply at the same time. Especially in advanced integrated logical circuits such as MPUs (micro processing units), in order to achieve these at the same time, the transistor performance has been increased and the current driving capability per channel width, i.e., unit area, has been enhanced.
A transistor having high current driving capability can obtain a sufficient output current in a smaller area, thus allowing for high integration.
In the meanwhile, still higher integration has been achieved by employing trench isolation as an element isolation means for electrically isolating a large number of elements. The trench isolation is a technique of electrically isolating elements by filling a trench disposed therebetween with an insulator. Recent advances in the technology of burying have made it possible to form a narrower and deeper element isolation insulating film.
FIG. 29 illustrates, in plan view, the construction of a semiconductor device 80 in which elements are electrically isolated from each other by trench isolation. Specifically, FIG. 29 is a fragmentary view when the semiconductor device 80 is seen from the top of its semiconductor substrate, and illustrates an arrangement of two MOS field effect transistors (hereinafter referred to as MOS transistors) M1 and M2.
The MOS transistors M1 and M2 are each surrounded by a trench isolation oxidation film and are electrically isolated from each other, and these are also electrically isolated from other semiconductor elements (not shown).
As shown in FIG. 29, the MOS transistor M1 has a larger channel width than the MOS transistor M2, and it comprises an elongated ate electrode 31 and a pair of source/drain regions 11 disposed in the semiconductor substrate surface located outside of the transversely opposite sides of the gate electrode 31. The gate electrode 31 at one end portion in the longitudinal direction is connected via a contact plug 51 to a wiring layer 61. The source/drain regions 11 are each connected via a plurality of contact plugs 511 to a wiring layer 611.
The MOS transistor M2 has an elongated gate electrode 32 and a pair of source/drain regions 12 disposed in the semiconductor substrate surface located outside of the transversely opposite sides of the gate electrode 32. The gate electrode 32 at one end portion in the longitudinal direction is connected via a contact plug 52 to a wiring layer 62. The source/drain regions 12 are each connected via a contact plug 521 to a wiring layer 621.
The constructions in cross section taken along line Axe2x80x94A and line Bxe2x80x94B in FIG. 29 are illustrated in FIG. 30 and FIG. 31, respectively.
As shown in FIGS. 30 and 31, the MOS transistors M1 and M2 are electrically isolated from each other by a trench isolation oxide film 20 formed in the surface of a semiconductor substrate 1.
In the MOS transistors M1 and M2, a gate oxide film 30 underlies the gate electrodes 31 and 32. The gate electrodes 31 and 32 are comprised of a polycrystalline silicon (doped polysilicon) which, for example, contains phosphorus of about 1xc3x971020 to 5xc3x971020/cm3 as impurity.
In FIGS. 30 and 31, the MOS transistors M1 and M2 are covered with an interlayer insulating film 40. The contact plugs 51, 52, 511 and 521 are disposed so as to extend through the interlayer insulating film 40, and the wiring layers 61, 62, 611 and 621 are disposed on the interlayer insulating film 40. Further, an interlayer insulating film (not shown) is disposed on the interlayer insulating film 40 and a wiring layer (not shown) is disposed on this interlayer insulating film. Thus, the wiring layers 61, 62, 611 and 621 are electrically connected to this wiring layer.
A method for manufacturing the semiconductor device 80 will be described by referring to FIGS. 32 to 38 illustrating a sequence of steps in the method. FIGS. 32 to 38 are cross sections taken along line Axe2x80x94A in FIG. 29.
In the step of FIG. 32, a silicon oxide film 3 and silicon nitride film 4 are formed on the entire surface of the semiconductor substrate 1. Then, by using a resist mask (not shown), the part of the silicon nitride film 4 and silicon oxide film 3 which corresponds to the region for forming an element isolation oxide film is selectively removed by anisotropic etching.
After the resist mask is removed, trenches 2 are formed by anisotropic etching by using the silicon nitride film 4 as a mask. This results in the construction of FIG. 32.
In the step of FIG. 33, damage by etching is recovered while the inner wall of the trenches 2 is covered with a silicon oxide film 10 by means of thermal oxidation.
In the step of FIG. 34, by CVD (chemical vapor deposition) method, a silicon oxide film 201 is formed on the entire surface so as to fill the trenches 2. Since the silicon oxide film 201 is formed so as to cover the silicon nitride film 4, the silicon oxide film 201 is left only in the trenches 2 and inside of the opening comprised of the silicon nitride film 4, by performing planarization with CMP (chemical mechanical polishing) process using the silicon nitride film 4 as a stopper.
In the step of FIG. 35, the silicon nitride film 4 and the underlying silicon oxide film 3 are removed to complete a trench isolation oxide film 20.
In the step of FIG. 36, a silicon oxide film is formed on the entire surface by thermal oxidation. Then, for instance, a polycrystalline silicon layer containing phosphorous is deposited on the enter surface by CVD method, and the polycrystalline silicon layer and silicon oxide film are patterned to form gate electrodes 31 and 32 and a gate oxide film 30. Subsequently, by ion implantation, impurity ion is implanted into the semiconductor substrate 1 such that source/drain regions (not shown) are formed in a self-aligned manner.
If required, the source/drain regions may be of LDD (lightly doped drain) structure by forming a side wall (not shown) and implanting additional impurity ion by ion implantation.
In the step of FIG. 37, a silicon oxide film is deposited on the entire surface thereby to form an interlayer insulating film 40. By using a resist mask (not shown), contact holes extending through the interlayer insulating film 40 to the gate electrode 31 or 32 are opened and the contact holes are then filled with a conductor layer, resulting in contact plugs 51 and 52.
FIG. 38 is a cross section taken along line Bxe2x80x94B of FIG. 29, and illustrates the state that contact plugs 511 and 521 reaching the semiconductor substrate 1 are formed. FIG. 39 illustrates, in plan view, the construction after passing through the steps of FIGS. 37 and 38.
Subsequently, a metal layer is deposited on the entire surface of the interlayer insulating film 40 and then patterned to form wiring layers 61, 62, 611 and 621, thereby obtaining the construction shown in FIGS. 30 and 31. In addition, an interlayer insulating film (not shown) is formed on the interlayer insulating film 40 and a wiring layer (not shown) is disposed on this interlayer insulating film. Thus, the wiring layers 61, 62, 611 and 621 are electrically connected to this wiring layer. Such illustration and description are omitted here.
The foregoing conventional semiconductor device 80 having the MOS transistors is constructed so that the main current passes through a channel formed in the surface of the semiconductor substrate 1 underlying the gate electrodes 31 and 32, and then flows between the paired source/drain regions 11 and source/drain regions 12.
Accordingly, the current driving capability is defined by the gate width of the MOS transistor unless the performance of the MOS transistors is increased. If more output current is needed, it is necessary to increase the occupied area of the MOS transistors. The result is that the area of the overall semiconductor device is increased, thus imposing limitation on integration.
As previously mentioned, instead of the conventional LOCOS (local oxidation of silicon) isolation by means of thermal oxidation, the trench isolation has been used as an element isolation means. The trench isolation is a means for effecting element isolation by digging a trench in a semiconductor substrate by etching and then filling the trench with an insulating film.
In this trench isolation, an element isolation oxide film having a width of 0.1 xcexcm is coming in practice by virtue of advances in the technology of burying an oxide film. However, the overall dimension of a semiconductor device using this element isolation oxide film is reduced only by the amount of the reduction in the isolation oxide film than that of a semiconductor device using the LOCOS isolation. This causes no change in the fact that the current driving capability of the MOS transistor is defined by the gate width.
According to a first aspect of the invention, a semiconductor device comprises: a semiconductor substrate; a MOS transistor disposed on the semiconductor substrate; and an element isolation insulating film for electrically isolating the MOS transistor from other semiconductor elements, disposed in a main surface of the semiconductor substrate, wherein the MOS transistor comprises a gate insulating film disposed on at least one active region defined as a region of the semiconductor substrate surrounded by the element isolation insulating film, and a gate electrode disposed on the gate insulating film, the element isolation insulating film has a groove portion disposed at the part bounded by the mentioned at least one active region, the side wall surface of the mentioned at least one active region is exposed in the groove portion, and the gate electrode is also disposed in the groove portion with the gate insulating film interposed therebetween.
According to a second aspect of the invention, the semiconductor device of the first aspect is characterized in that the mentioned at least one active region is a plurality of active regions arranged at spaced intervals along the direction in which the gate electrode extends, the active regions being electrically isolated from each other by the element isolation insulating film, and the groove portion is also disposed in the element isolation insulating film for isolating the active regions.
According to a third aspect of the invention, the semiconductor device of the first aspect further comprises at least one local insulating film disposed in the surface of the semiconductor substrate underlying the gate electrode in the mentioned at least one active region, wherein the mentioned at least one local insulating film has a groove portion disposed at the part bounded by the mentioned at least one active region around the local insulating film, and the side wall surface of the mentioned at least one active region is exposed in the groove portion.
According to a fourth aspect of the invention, the semiconductor device of the second or third aspect is characterized in that in the opening of the groove portion, the depth dimension along the side wall surface is greater than the width dimension of the top.
According to a fifth aspect of the invention, the semiconductor device of the fourth aspect is characterized in that the cross-sectional shape of the upper edge portion of the mentioned at least one active region is in a circular arc.
According to a sixth aspect of the invention, the semiconductor device of the second aspect is characterized in that in the element isolation insulating film for isolating the active regions, the width dimension along the direction of extension of the gate electrode is smaller than twice the depth dimension along the side wall surface of the groove portion.
According to a seventh aspect of the invention, the semiconductor device of the third aspect is characterized in that in the local insulating film, the width dimension along the direction of extension of the gate electrode is smaller than twice the depth dimension along the side wall surface of the groove portion.
According to an eighth aspect of the invention, a method for manufacturing a semiconductor device having a MOS transistor comprises the steps of: (a) forming a trench defining at least one active region in a main surface of a semiconductor substrate; (b) burying an insulating film in the trench; (c) planarizing the insulting film; (d) reducing the thickness of the insulting film by isotropic etching so as to have approximately the same height as the main surface of the mentioned at least one active region, and forming a groove portion at the boundary part between the insulating film and the mentioned at least one active region so as to expose the side wall surface of the mentioned at least one active region; and (e) forming a gate insulating film and a gate electrode of the MOS transistor on the mentioned at least one active region.
According to a ninth aspect of the invention, the method of the eighth aspect is characterized in that: the step (a) includes the steps of forming a silicon oxide film and a silicon nitride film in sequence on the main surface of the semiconductor substrate and forming the trench by selectively etching the silicon oxide film, the silicon nitride film and the semiconductor substrate; the step (c) includes the step of planarizing the insulating film by using the silicon nitride film as a stopper; and the step (d) includes the step in which the silicon nitride film serving as the stopper is removed to form a recess portion on the surface of the insulating film, followed by the isotropic etching.
According to a tenth aspect of the invention, the method of the eight aspect further comprises the step, after the step (d), of performing an oblique ion implantation to the mentioned at least one active region.
According to an eleventh aspect of the invention, the method of the tenth aspect is characterized in that the oblique ion implantation includes the step of performing the ion implantation a number of times with the semiconductor substrate inclined with respect to the direction of transport of ion beams.
According to a twelfth aspect of the invention, the method of the eleventh aspect is characterized in that the step of performing the oblique ion implantation a number of times includes the steps of: performing the ion implantation each time the semiconductor substrate is intermittently rotated in the plane a predetermined angle; and setting a rotational number N such that the angle of inclination xcex8 of the semiconductor substrate and the intermittent rotational number N of the semiconductor substrate satisfy the relationship of N=1/COS xcex8.
According to a thirteenth aspect of the invention, the method of the twelfth aspect is characterized in that the ion implantation step is the step, before the step (e), of performing ion implantation for determining the threshold value of the MOS transistor.
According to a fourteenth aspect of the invention, the method of the twelfth aspect is characterized in that the ion implantation step is the step, after the step (f), of performing ion implantation for forming the source/drain regions of the MOS transistor.
According to a fifteenth aspect of the invention, the method of the eighth aspect further comprises the step, before the step (b), of subjecting the inner surface of the trench to thermal oxidation, wherein, by the thermal oxidation step, the cross-sectional shape of the upper edge portion of the mentioned at least one active region is formed into a circular arc.
According to a sixteenth aspect of the invention, the method of the fifteenth aspect is characterized in that the thermal oxidation step includes a high temperature thermal oxidation step conducted in an atmosphere containing oxygen at a temperature of 1000 to 1200xc2x0 C.
According to a seventeenth aspect of the invention, the method of the eighth aspect further comprises the step, before the step (b), of hydrogen annealing step conducted in a hydrogen atmosphere at a temperature of 850 to 1000xc2x0 C., wherein, by the hydrogen annealing step, the cross-sectional shape of the upper edge portion of the mentioned at least one active region is formed into a circular arc.
In the semiconductor device of the first aspect, the element isolation insulating film has the groove portion disposed at the part bounded by at least one active region, and the wall surface of at least one active region is exposed in the groove portion, and the gate electrode is also disposed in the groove portion with the gate insulting film. Therefore, the side wall part of at least one active region can also be used as a channel region. This enables to increase the current driving capability of the MOS transistor without increasing the gate width, and thus permitting the semiconductor device that can obtain more output current without increasing the occupied area of the MOS transistor. In addition, since the groove portion is merely disposed at the boundary part between the element isolation insulating film and at least one active region, the surface of the gate electrode disposed thereon can be planarized. This increases the dimensional accuracy at the time of photolithography, thus permitting the MOS transistor causing less variations in transistor characteristic.
In the semiconductor device of the second aspect, at least one active region is provided as a plurality of active regions arranged at spaced intervals along the direction in which the gate electrode extends, and the groove portion is also disposed in the element isolation insulating film for isolating a plurality of active regions. Thereby, the effective channel region width can be further increased and the current driving capability can be increased to permit higher speed operation. In addition, since the current driving capability per unit area is increased, the MOS transistor can be further minimized to reduce the chip size.
In the semiconductor device of the third aspect, at least in one active region, at least one local insulating film is disposed in the surface of the semiconductor substrate underlying the gate electrode, and the groove portion is also provided at the boundary part between the local insulating film and the active region therearound. Thereby, the effective channel region width can be further increased and the current driving capability can be increased to permit higher speed operation. In addition, because at least one active region is basically of unitary configuration, wide source/drain regions can be obtained to increase the degree of freedom of the contact hole disposition with respect to the source/drain regions. As a result, the design margin is increased and a further reduction in chip size can be expected.
In the semiconductor device of the fourth aspect, the groove portion of the element isolation insulating film for isolating a plurality of active regions has the opening in which the depth dimension along the sidewall surface is greater than the width of the top. This permits a further increase in the effective channel region width.
In the semiconductor device of the fifth aspect, the upper edge portion of at least one active region is rounded by increasing its radius of curvature. This enables to prevent the reverse narrow channel effect caused by the fringing field from the gate electrode.
In the semiconductor device of the sixth aspect, in the element isolation insulating film for isolating a plurality of active regions, the width dimension along the direction of extension of the gate electrode is smaller than twice the depth dimension along the sidewall surface of the groove portion. Thereby, the channel region at the side wall part of each active region is larger than the width dimension of the element isolation insulating film, thus permitting a further increase in the effective channel region width.
In the semiconductor device of the seventh aspect, the width dimension along the direction of extension of the gate electrode in the local insulating film is smaller than twice the depth dimension along the sidewall surface of the groove portion. Thereby, the channel region at the side wall part of each active region is larger than the width dimension of the local insulating film, thus permitting a further increase in the effective channel region width.
With the method of the eighth aspect, it is able to obtain the semiconductor device in which the element isolation insulating film has the groove portion disposed at the part bounded by at least one active region, and the side wall surface of at least one active region is exposed in the groove portion, and the gate electrode is also disposed in the groove portion with the gate insulating film.
With the method of the ninth aspect, the groove portion can be reliably formed at the boundary part between the insulating film and at least one active region by removing the silicon nitride film used as a stopper, to form the recess part in the surface of the insulating film, followed by isotropic etching in an over etching fashion.
With the method of the tenth aspect, ion implantation can be performed to the exposed side wall surface of at least one active region, thereby the side wall part of the active region can be used as a channel region.
With the method of the eleventh aspect, ion implantation can be performed reliably to the exposed side wall surface of at least one active region.
With the method of the twelfth aspect, when the semiconductor substrate is inclined at an angle xcex8, the dose to the planarized part is reduced than that would be the case without inclining the semiconductor substrate, however, a predetermined dose is obtainable by setting the number of rotations N so as to satisfy the relationship of N=1/COS xcex8.
With the method of the thirteenth aspect, it is able to implant a predetermined amount of ion for determining the threshold value of the MOS transistor.
With the method of the fourteenth aspect, it is able to implant a predetermined amount of ion for forming the source/drain regions of the MOS transistor.
With the method of the fifteenth aspect, the upper edge portion of at least one active region can be formed into a circular arc by the step of subjecting the inner surface of the trench to thermal oxidation. It is therefore able to suppress the manufacturing steps from being complicated in order to obtain the semiconductor device preventing the reverse narrow channel effect caused by the fringing field from the gate electrode.
With the method of the sixteenth or seventeenth aspect, the upper edge portion of at least one active region can be reliably formed into a circular arc.
It is an object of the present invention to overcome the foregoing drawbacks by providing a semiconductor device capable of obtaining more output current without increasing the occupied area of a MOS transistor, as well as a method for manufacturing the same.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.